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march 2011 FDMS7620S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 1 www.fairchildsemi.com FDMS7620S rev.c1 FDMS7620S dual n-channel powertrench ? mosfet q1: 30 v, 10.1 a, 20.0 m q2: 30 v, 12.4 a, 11.2 m features q1: n-channel ? max r ds(on) = 20.0 m at v gs = 10 v, i d = 1 0.1 a ? max r ds(on) = 30.0 m at v gs = 4.5 v, i d = 7.5 a q2: n-channel ? max r ds(on) = 11.2 m at v gs = 10 v, i d = 12.4 a ? max r ds(on) = 14.2 m at v gs = 4.5 v, i d = 10.9 a ? pinout optimized for simple pcb design ? thermally efficient dual power 56 package ? rohs compliant general description this device includes two specialized mosfets in a unique dual power 56 package. it is designed to provide an optimal synchro - nous buck power stage in terms of efficiency and pcb utilization. the low switching loss ?high si de? mosfet is complementory by a low conduction loss ?low side? syncfet. applications synchronous buck converter for: ? notebook system power ? general purpose point of load power 56 s2 s2 s2 g2 d1 d1 d1 g1 d1 s1/d2 top bottom pin1 4 3 2 1 5 6 7 8 q 1 q 2 mosfet maximum ratings t a = 25c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter q1 q2 units v ds drain to source voltage 30 30 v v gs gate to source voltage (note 3) 20 20 v i d drain current -continuous (package limited) t c = 25 c 13 22 a -continuous (silicon limited) t c = 25 c 26 42 -continuous t a = 25 c 10.1 12.4 -pulsed 27 45 e as single pulse avalanche energy (note 4) 9 21 mj p d power dissipation for single operation t a = 25c 2.2 1a 2.5 1b w power dissipation for single operation t a = 25c 1.0 1c 1.0 1d t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient 57 1a 50 1b c/w r ja thermal resistance, junction to ambient 125 1c 120 1d device marking device package reel size tape width quantity FDMS7620S FDMS7620S power 56 13 ? 12 mm 3000 units
FDMS7620S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 2 www.fairchildsemi.com FDMS7620S rev.c1 electrical characteristics t j = 25c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics symbol parameter test conditions type min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v i d = 1 ma, v gs = 0 v q1 q2 30 30 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25c i d = 10 ma, referenced to 25c q1 q2 19 19 mv/c i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v q1 q2 1 500 a i gss gate to source leakage current, forward v gs = 20 v, v ds = 0 v q1 q2 100 100 na na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a v gs = v ds , i d = 1 ma q1 q2 1.0 1.0 2.2 2.0 3.0 3.0 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25c i d = 10 ma, referenced to 25c q1 q2 -6 -5 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 10.1 a v gs = 4.5 v, i d = 7.5 a v gs = 10 v, i d = 10 a, t j = 125c q1 15.2 22.7 18.7 20.0 30.0 22.5 m v gs = 10 v, i d = 12.4 a v gs = 4.5 v, i d = 10.9 a v gs = 10 v, i d = 12.4 a, t j = 125c q2 8.3 10.5 8.9 11.2 14.2 15.1 g fs forward transconductance v dd = 5 v, i d = 10.1 a v dd = 5 v, i d = 12.4 a q1 q2 22 53 s c iss input capacitance v ds = 15 v, v gs = 0 v, f = 1 mhz q1 q2 457 1050 608 1400 pf c oss output capacitance q1 q2 167 358 222 477 pf c rss reverse transfer capacitance q1 q2 22 35 31 49 pf r g gate resistance q1 q2 0.2 0.2 1.6 1.2 4.4 3.5 t d(on) turn-on delay time q1 v dd = 15 v, i d = 10.1 a, r gen = 6 q2 v dd = 15 v, i d = 12.4 a, r gen = 6 q1 q2 5.2 6.6 10 14 ns t r rise time q1 q2 1.2 1.8 10 10 ns t d(off) turn-off delay time q1 q2 11.9 17.4 22 32 ns t f fall time q1 q2 1.4 1.5 10 10 ns q g(tot) total gate charge v gs = 0v to 10 v q1 v dd = 15 v, i d = 10.1 a q1 q2 7.2 15.6 11 23 nc q g(tot) total gate charge v gs = 0v to 5 v q1 q2 3.8 7.9 6 12 nc q gs gate to source charge q2 v dd = 15 v, i d = 12.4 a q1 q2 1.6 3.2 nc q gd gate to drain ?miller? charge q1 q2 1.1 1.6 nc
FDMS7620S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 3 www.fairchildsemi.com FDMS7620S rev.c1 electrical characteristics t j = 25c unless otherwise noted drain-source diod e characteristics notes: 1. r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. as an n-ch device, the negative vgs rating is for low duty cycle pulse ocurrence only. no continuous rating is implied. 4. q1: e as of 9 mj is based on starting t j = 25 o c, l = 0.3 mh, i as = 8 a, v dd = 27 v, v gs = 10 v. 100% test at l = 3 mh, i as = 2.0 a, v dd = 0 v, v gs = 15 v. q2: e as of 21 mj is based on starting t j = 25 o c, l = 0.3 mh, i as = 12 a, v dd = 27 v, v gs = 10 v. 100% test at l = 3 mh, i as = 3.2a, v dd = 0 v,v gs = 15 v.. symbol parameter test conditions type min typ max units v sd source-drain diode forward voltage v gs = 0 v, i s = 10.1 a (note 2) v gs = 0 v, i s = 12.4 a (note 2) q1 q2 0.90 0.83 1.2 1.2 v t rr reverse recovery time q1 i f = 10.1 a, di/dt = 100 a/s q2 i f = 12.4 a, di/dt = 300 a/s q1 q2 16 18 28 32 ns q rr reverse recovery charge q1 q2 4 13 10 23 nc a. 57 c/w when mounted on a 1 in 2 pad of 2 oz copper c. 125 c/w when mounted on a minimum pad of 2 oz copper b. 50 c/w when mounted on a 1 in 2 pad of 2 oz copper d. 120 c/w when mounted on a minimum pad of 2 oz copper
FDMS7620S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 4 www.fairchildsemi.com FDMS7620S rev.c1 typical characteristics (q1 n-channel) t j = 25c unless otherwise noted figure 1. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 3 6 9 12 15 18 21 24 27 v gs = 6 v v gs = 4 v v gs = 10 v v gs = 4.5 v v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5% max i d , drain current (a) v ds , drain to source voltage (v) on region characteristics figure 2. 0 3 6 9 12 15 18 21 24 27 0 1 2 3 4 5 6 v gs = 6 v v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 4 v v gs = 4.5 v v gs = 10 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = 10.1 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 345678910 0 10 20 30 40 50 60 t j = 125 o c i d = 10.1 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 3 6 9 12 15 18 21 24 27 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 30 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDMS7620S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 5 www.fairchildsemi.com FDMS7620S rev.c1 figure 7. 02468 0 2 4 6 8 10 i d = 10.1 a v dd = 20 v v dd = 10 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 15 v gate charge characteristics figure 8. 0.1 1 10 30 10 100 1000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.001 0.01 0.1 1 10 1 10 20 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability figure 10. 0.01 0.1 1 10 100200 0.01 0.1 1 10 50 100 p s dc 100 ms 10 ms 1 ms 1s i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds ( on ) single pulse t j = max rated r t ja = 125 o c/w t a = 25 o c 10s f o r w a r d b i a s s a f e operating area figure 11. 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.1 1 10 100 1000 p (pk) , peak transient power (w) single pulse r t ja = 125 o c/w t, pulse width (sec) single pulse maximum power dissipation typical characteristics (q1 n-channel) t j = 25c unless otherwise noted
FDMS7620S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 6 www.fairchildsemi.com FDMS7620S rev.c1 figure 12. 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.001 0.001 0.01 0.1 1 2 single pulse r t ja = 125 o c/w (note 1b) duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a junction-to-ambient transient thermal response curve typical characteristics (q1 n-channel) t j = 25c unless otherwise noted
FDMS7620S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 7 www.fairchildsemi.com FDMS7620S rev.c1 typical characteristics (q2 n-channel) t j = 25 c unless otherwise noted figure 13. on-region characteristics figure 14. normalized on-resistance vs drain current and gate voltage figure 15. normalized on-resistance vs junction temperature figure 16. on-resistance vs gate to source voltage figure 17. transfer characteristics figure 18. source to drain diode forward voltage vs source current 0.0 0.5 1.0 1.5 2.0 0 9 18 27 36 45 v gs = 4 v v gs = 6 v v gs = 10 v v gs = 4.5 v v gs = 3.5 v pulse duration = 80 s duty cycle = 0.5% max i d , drain current (a) v ds , drain to source voltage (v) 0 9 18 27 36 45 0 2 4 6 v gs = 6 v v gs = 3.5 v pulse duration = 80 s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 4 v v gs = 4.5 v v gs = 10 v -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = 12.4 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) 246810 4 8 12 16 20 24 28 t j = 125 o c i d = 12.4 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m pulse duration = 80 s duty cycle = 0.5% max 1.5 2.0 2.5 3.0 3.5 4.0 0 9 18 27 36 45 t j = 125 o c v ds = 5 v pulse duration = 80 s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 50 t j = -55 o c t j = 25 o c t j = 125 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v)
FDMS7620S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 8 www.fairchildsemi.com FDMS7620S rev.c1 typical characteristi cs (q2 n-channel) t j = 25c unless otherwise noted figure 19. gate charge characteristics figure 20. capacitance vs drain to source voltage figure 21. unclamped inductive switching capability f i g u r e 2 2 . f o r w a r d b i a s s a f e operating area figure 23. single pulse maximum power dissipation 0 5 10 15 20 0 2 4 6 8 10 i d = 12.4 a v dd = 20 v v dd = 10 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 15 v 0.1 1 10 10 100 1000 3000 30 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss 0.001 0.01 0.1 1 10 30 1 10 30 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) 0.01 0.1 1 10 100200 0.01 0.1 1 10 70 100 s dc 100 ms 10 ms 1 ms 1s i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds ( on ) single pulse t j = max rated r ja = 120 o c/w t a = 25 o c 10s 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.1 1 10 100 1000 p (pk) , peak transient power (w) single pulse r ja = 120 o c/w t, pulse width (sec)
typical characteristics (q2 n-channel) t j = 25 c unless otherwise noted figure 24. junction-to-ambient transient thermal response curve 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.001 0.01 0.1 1 2 single pulse r t ja = 120 o c/w (note 1b) duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a FDMS7620S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 9 www.fairchildsemi.com FDMS7620S rev.c1
FDMS7620S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 10 www.fairchildsemi.com FDMS7620S rev.c1 syncfet schottky body diode characteristics fairchild?s syncfet process emb eds a schottky diode in parallel with powertrench mosfet. th is diode exhibits similar characteristics to a discrete exte rnal schottky diode in parallel with a mosfet. figure 26 shows the reverse recovery characteristic of the FDMS7620S. schottky barrier diodes exhibit significant leakage at high tem- perature and high reverse voltage. this will increase the power in the device. 0 50 100 150 200 -5 0 5 10 15 current (a) time (ns) di/dt = 300 a/ s 0 5 10 15 20 25 30 10 -6 10 -5 10 -4 10 -3 10 -2 t j = 125 o c t j = 100 o c t j = 25 o c i dss , reverse leakage current (a) v ds , reverse voltage (v) typical characteristics (continued) figure 25. FDMS7620S syncfet body diode reverse recovery characteristic figure 26. syncfet body diode reverse leakage versus drain-source voltage
FDMS7620S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 11 www.fairchildsemi.com FDMS7620S rev.c1 dimensional outlin e and pad layout 6. 30 0.63 1.27 1. 27 (opti on 2 - isolated leads) (opti on 1 - fused l eads 5,6 ,7) 0.20 0.340 4x r ecomm end ed la nd pat t ern 2. 67 4.00 0. 65 t yp 12 3 4 5 6 7 8 0.92 0. 66 0. 54 0. 40 0.65 (5x) 0.63 3. 81 1. 27 6.0 5. 0 pin# 1 quad ran t 0.80 max 0. 25 0 b. dimensions are in mill imeters. c. dimensions and tolerances per e. drawing file name : mkt-mlp08prev1 a. does not ful ly conform to jedec regist rat ion, m o- 229. asme y14. 5m, 19 94 top view b ottom view r ecomm end ed la nd pat t ern 0. 08 c b a 0. 10 c 2x 0.10 c 2x side vi ew (0.20 ) seating pl ane 0. 10 c a b 0. 10 c 12 3 4 5 6 7 8 6. 30 2. 67 4.00 0. 65 t yp pin #1 ident 0. 05 c 1 2 3 4 5 6 7 8 0. 05 0. 00 2.72 2.62 3. 85 3. 75 0. 48 0. 38 (5x) 0. 97 0. 87 0. 56 0. 46 (5 x) 0.92 0. 66 0. 66 0. 55 0. 54 0. 40 0. 45 d. l and patt ern rec ommen dat ion is based on fsc design only
FDMS7620S dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation 12 www.fairchildsemi.com FDMS7620S rev.c1 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairch ild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of th e application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the term s of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized fo r use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used here in: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms accupower? 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